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SG6741A -- Highly Integrated Green-Mode PWM Controller
April 2008
SG6741A -- Highly Integrated Green-Mode PWM Controller
Features
High-voltage Startup Low Operating Current: 4mA Linearly Decreasing PWM Frequency to 18kHz Frequency Hopping to Reduce EMI Emissions Peak-current-mode Control Cycle-by-cycle Current Limiting Leading-edge Blanking (LEB) Synchronized Slope Compensation GATE Output Maximum Voltage Clamp: 18V VDD Over-voltage Protection (Auto Restart) VDD Under-voltage Lockout (UVLO) Internal Open-loop Protection Constant Power Limit (Full AC Input Range)
Description
The highly integrated SG6741A series of PWM controllers provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 18KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is eliminated. To further reduce power consumption, SG6741A is manufactured using the BiCMOS process, which allows an operating current of only 4mA. SG6741A integrates a frequency-hopping function internally to reduce EMI emission of a power supply with minimum line filters. A built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal line compensation ensures constant output power limit over a wide AC input voltages, from 90VAC to 264VAC. SG6741A provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety when an open-loop or output short-circuit failure occurs. PWM output is disabled until VDD drops below the UVLO lower limit, when the controller starts up again. As long as VDD exceeds ~26V, the internal OVP circuit is triggered. SG6741A is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS
Ordering Information
Part Number
SG6741ASZ
Operating Temperature Range
-20 to +85C
Package
8-Lead Small Outline Package (SOP)
Packing Method
Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 1. Typical Application
Block Diagram
Figure 2. Block Diagram
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
Marking Information
T: S = SOP P: Z =Lead Free Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location
SG6741ATP XXXXXXXXYWWV
Figure 3. Top Mark
Pin Configuration
GND FB NC HV GATE VDD SENSE
RI
Figure 4. Pin Configuration
Pin Definitions
Pin #
1 2 3 4
Name
GND FB NC HV
Description
Ground. Feedback. The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on SENSE pin. No Connection. Start-up Input. For start-up, this pin is pulled HIGH to the line input or bulk capacitor via resistors. Reference Setting. A resistor connected from the RI pin to GND pin provides a constant current source, which determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K resistor for RI results in a 65kHz center PWM frequency. Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. Driver Output. The totem-pole output driver. Soft driving waveform is implemented for improved EMI.
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5
RI
6 7 8
SENSE VDD GATE
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
SG6741A -- Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the ground pin.
Symbol
VDD VHV VL PD JA TJ TSTG TL ESD Supply Voltage
Parameter
Input Voltage to HV Pin Input Voltage to FB, SENSE, Pin Power Dissipation, TA < 50C Thermal Resistance (Junction-to Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model, JESD22-A114 Machine Model, JESD22-A115
Min.
Max.
30 500
Unit
-.3
7.0 400 141 mW C/W C C C
-40 -55
+125 +150 +260 3 250
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-20
Max.
+85
Unit
C
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD = 15V; TA = 25, unless otherwise noted.
VDD Section
Symbol
VDD-OP VDD-ON VDD-OFF IDD-ST IDD-OP IDD-OLP VDD-OLP VDD-OVP tD-VDDOVP
Parameter
Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage Startup Current Operating Supply Current Internal Sink Current IDD-OLP off Voltage VDD Over-Voltage Protection VDD Over-Voltage Protection Debounce Time
Conditions
Min.
15.5 9.5
Typ.
16.5 10.5
Max.
22 17.5 11.5 30
Units
V V V A mA A V V s
VDD-ON - 0.16V VDD = 15V GATE Open VDD-OLP +0.1V Auto Restart Auto Restart 50 6.5 25 100 4 70 7.5 26 180
5 90 8.0 27 260
HV Electrical Characteristics
Symbol
IHV IHV-LC
Parameter
Supply Current Drawn from HV Pin Leakage Current After Startup
Conditions
VAC=90V (VDC=120V), VDD=10F HV=500V, VDD=VDD-OFF+1V
Typ.
2 1
Max.
Units
mA
20
A
Oscillator Section
Symbol
fOSC tHOP fOSC-G fDV fDT
Parameter
Frequency in Nominal Mode Hopping Period Green-Mode Frequency
Conditions
Center Frequency Hopping Range
Min.
62 3.7 16
Typ.
65 4.2 4.4 18
Max.
68 4.7 21 5 5
Units
kHz ms kHz % %
Frequency Variation vs. VDD Deviation VDD=11V to 22V Frequency Variation vs. Temperature Deviation TA=-20 to 85C
Feedback Input Section
Symbol
AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N VFB-G VFB-ZDC
Parameter
Input Voltage to Current-Sense Attenuation Input Impedance FB Output High Voltage FB Open-loop Trigger Level
Conditions
Min.
1/3.75 4
Typ.
Max.
Units
V/V k V V ms V V V
1/3.20 1/2.75 7 4.0
56 2.1
FB Pin Open
5.5 3.7
50 1.9
4.3
62 2.3
The Delay Time of FB Pin Open-Loop RI=26k Protection Green-Mode Entry FB Voltage Green-Mode Ending FB Voltage Zero Duty-Cycle Input Voltage
VFB-N 0.5 1
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
PWM Frequency
PWM Frequency
f OSC
f OSC -
V FB-ZDC V FB-G
V FB-N
VFB
Figure 5. PWM Frequency
Current-Sense Section
Symbol
ZSENSE VSTHFL VSTHVA tPD tLEB Input Impedance Current Limit Flatten Threshold Voltage Current Limit Valley Threshold Voltage Delay to Output Leading-Edge Blanking Time 275 VSTHFL-VSTHVA 0.87 0.18
Parameter
Conditions
Min.
Typ.
12 0.90 0.22 100 350
Max.
0.93 0.26 200 425
Units
K V V ns ns
Gate Section
Symbol
DCYMAX VGATE-L VGATE-H tr tf
Parameter
Maximum Duty Cycle Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time
Conditions
VDD=15V, IO=50mA VDD=12.5V, IO=-50mA VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=15V, GATE=6V VDD=22V
Min.
60 8 150 30 250
Typ.
65
Max.
70 1.5
Units
% V V ns ns mA V %
250 50
350 90 18
IGATE-SOURCE Gate Source Current VGATE-CLAMP Gate Output Clamping Voltage DCYMAX Maximum Duty Cycle
60
65
70
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
25
5. 0
20
4. 0
IDD -ST (A)
IDD-OP (mA)
15
3. 0
10
2. 0
5
1. 0
0 40 25 10 5 20 35 50 65 80 95 110 125
0. 0 40 25 10 5 20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C )
Figure 6. Startup Current (IDD-ST) vs. Temperature
20. 0 19. 0 18. 0 17. 0 16. 0 15. 0 40 25 10 5 20 35 50 65 80 95 110 125
Figure 7. Operating Supply Current (IDD-OP) vs. Temperature
13. 0
12. 0
VDD -OFF (V)
VDD -ON (V)
11. 0 10. 0
9. 0
8. 0 40 25 10 5 20 35 50 65 80 95 110 125
Temperature ( C )
Temperature (C)
Figure 8. Start Threshold Voltage (VDD-ON) vs. Temperature
5. 0
Figure 9. Minimum Operating Voltage (VDD-OFF) vs. Temperature
10
4. 0 3. 0
8
IHV (mA)
2. 0 1. 0
IHV-LC (A)
40 25 10 5 20 35 50 65 80 95 110 125
6
4
2
0. 0
0 40 25 10 5 20 35 50 65 80 95 110 125 Tem perature ( C )
Temperature (C)
Figure 10. Supply Current Drawn from HV Pin (IHV) vs. Temperature
70
Figure 11. Figure Caption
70. 0
68
68. 0
66
DCYM AX (%)
f OSC (kHz)
66. 0
64
64. 0
62
62. 0
60 40 25 10 5 20 35 50 65 80 95 110 125
60. 0 40 25 10 5 20 35 50 65 80 95 110 125
Temperature (C )
Temperature (C )
Figure 12. Frequency in Nominal Mode (fOSC) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0 7
Figure 13. Maximum Duty Cycle (DCYMAX) vs. Temperature
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SG6741A -- Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current
For start-up, the HV pin is connected to the line input or bulk capacitor through an external resistor, RHV, which is recommended as 100K. Typical startup current drawn from pin HV is 2mA and charges the hold-up capacitor through the resistor RHV. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the SG6741A to maintain VDD before the auxiliary winding of the main transformer provides the operating current.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.
Under-voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 16.5V and 10.5V. During startup, the hold-up capacitor must be charged to 16.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10.5V during startup. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup.
Operating Current
Operating current is around 4mA. The low operating current enables a better efficiency and reduces the requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides an offtime modulation to reduce the switching frequency in the light-load and no-load conditions. The on-time is limited for better abnormal or brownout protection. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency around 18KHz (RI=26K).
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction is avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI.
Oscillator Operation
A resistor connected from the RI pin to the GND pin generates a constant current source for the controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K resistor RI results in a corresponding 65KHz PWM frequency. The relationship between Ri and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability or prevents sub-harmonic oscillation. SG6741A inserts a synchronized positive-going ramp at every switching cycle.
fPWM
=
1690 (KHz) RI (K )
Constant Output Power Limit
When the SENSE voltage, across the sense resistor Rs, reaches the threshold voltage, around 0.9V, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD * VIN / LP. Since the delay is nearly constant, regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than that under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs.
(1)
The range of the PWM oscillation frequency is designed as 47kHz ~ 109kHz.
Current Sensing and PWM Current Limiting
Peak-current-mode control is utilized in SG6741A to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB-1.2)/3.2, a switch cycle terminates immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit.
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
VDD Over-voltage Protection (OVP)
VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP) and lasts for tD-VDDOVP, the PWM pulses are disabled until the VDD voltage drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops.
When VDD goes below the turn-off threshold (~10.5V) the controller is totally shut down. VDD is charged up to the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions.
Noise Immunity
Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG6741A, and increasing the power MOS gate resistance improve performance.
Limited Power Control
The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing.
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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)
SG6741A -- Highly Integrated Green-Mode PWM Controller
Reference Circuit
2 BD1 2 4 2 CN1 1 2 3 1 3 CN1 L1 T1 4 VZ1 C1 C2 1 3 4 1 2 4 5 6 2 1 T2 8 3 + 3 C4 2 2 1 + C7 1 1 3 7 + C8 1 3 D1 C3 C5 R1 Q1 1 L4 VO+ 2 2 L2 4 1 VO+ 1 2 R2 C6
D2
2
VO2 R3 2 R4 1 3 D3 1 2 + U1 1 2 C12 3 4 GND FB NC HV SG6741A GATE VDD SENSE RI 8 7 6 5 R6 C10 R5 1 C9 2 R7 U2 R8 4 1 Q2
VO+
R9 3 K2 C11 R U3 A
R10
R11
Figure 14. Circuit (12V/5A)
BOM
Reference
BD1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 F1 L1 Q1
BD 4A/600V XC 0.68F/300V XC 0.1F/300V YC 222pF/Y1 EC 120F/400V CC 0.01F/500V CC 102pF/100V EC 1000F/25V EC 470F/25V EC 22F/50V CC 470pF/50V CC 222pF/50V CC 103pF/50V Zener Diode 15V 1/2W (option) BYV95C FR103 FUSE 4A/250V 900H STP20-100CT
Component
Reference
Q2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 T1 T2 U1 U2 U3 VZ1 MOS 7A/600V R 100K 1/2W R 47 1/4W R 100K 1/2W R 20 1/8W R 100 1/8W R 33K 1/8W R 0.3 2W R 680 m 1/8W R 4.7K 1/8W
Component
R 150K m 1/8W R 39K 1/8W 10mH 600H(PQ2620) IC SG6741A IC PC817 IC TL431 VZ 9G
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
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SG6741A -- Highly Integrated Green-Mode PWM Controller
Physical Dimensions
8 5 C
1 b
4 e
D
A1
A
Figure 15. 8-Lead Small Outline Package (SOP)
Dimensions
Millimeter Symbol Min.
A A1 b c D E e F H L 1.346 0.101 0.406 0.203 4.648 3.810 1.016 5.791 0.406 0 4.978 3.987 1.524 6.197 1.270 8 0.183 0.150 0.040 0.228 0.016 0
Typ.
1.270 0.381X45
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2008 Fairchild Semiconductor Corporation SG6741A * Rev. 1.0.0
H F
E
L
Inch Max.
1.752 0.254
Min.
0.053 0.004
Typ.
Max.
0.069 0.010
0.016 0.008 0.196 0.157 0.060 0.244 0.050 8
0.050 0.015X45
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SG6741A -- Highly Integrated Green-Mode PWM Controller
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